74LVC1G08GV,125

74LVC1G08GV,125 is a single 2-input AND gate. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as translator in mixed 3.3V and 5V applications. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall time. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. It complies with JEDEC standard (JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• Wide supply voltage range from 1.65V to 5.5V
• High noise immunity, ±24mA output drive (VCC = 3V)
• CMOS low power dissipation, direct interface with TTL levels
• Overvoltage tolerant inputs to 5.5V, IOFF circuitry provides partial power-down mode operation
• Latch-up performance ≤ 250mA, input leakage current is ±0.1μA typical
• Supply current is 0.1μA typ at (VI = 5.5V or GND; IO = 0A; VCC = 1.65V to 5.5V, -40 °C to +85 °C)
• Input capacitance is 5pF typical at (VCC = 3.3V; VI = GND to VCC, -40°C to +85°C)
• Propagation delay is 3.4ns typical at (VCC = 1.65V to 1.95V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• 5-lead SC-74A package

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